In modern processor implementations, variations in process, voltage, and temperature (PVT) can cause malfunctions. PVT variations may become more pronounced as processors scale-up. On-die temperature variation is one of many PVT-related problems that can cause problems in processors, systems on a chip, application specific integrated circuits, etc. On-die temperature variation refers to a temperature gradient in different parts of a chip. In some instances, temperature variation leads to “hotspots” within a chip, where certain areas exhibit significantly higher temperatures than nearby areas. In some instances, hotspots may result from clustering high-activity networks and connected devices in certain areas. Under many workloads, the clustered high-activity networks may cause hotspots on the chip. These hotspots can negatively affect chip performance, such as by causing EM/IR issues, NBTI/PBTI issues, additional leakage power dissipation (e.g., leakage power may almost double with every 10 C rise in temperature).
In modern sign-off processes, designers typically focus on timing, power sign-off, and some reliability issues. However, thermal issues may be left largely unaddressed.